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Final Electrical Specifications
FEATURES
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LTC3708 Fast 2-Phase, No RSENSE Buck Controller with Output Tracking November 2003 DESCRIPTIO
The LTC(R)3708 is a dual, 2-phase synchronous step-down switching regulator with output voltage up/down tracking capability. The IC allows either coincident or ratiometric tracking. Multiple LTC3708s can be daisy-chained in applications requiring more than two voltages to be tracked. Power supply sequencing is accomplished using an external soft-start timing capacitor. The LTC3708 uses a constant on-time, valley current mode control architecture to deliver very low duty factors without requiring a sense resistor. Operating frequency is selected by an external resistor and is compensated for variations in input supply voltage. An internal phase-locked loop allows the IC to be synchronized to an external clock. Fault protection is provided by an output overvoltage comparator and an optional short-circuit shutdown timer. The regulator current limit level is user programmable. A wide supply range allows voltages as high as 36V to be stepped down to 0.6V output.
, LTC and LT are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation.
Very Low Duty Factor Operation (tON(MIN) < 85ns) No RSENSETM Option for Maximum Efficiency Very Fast Transient Response Programmable Output Voltage Up/Down Tracking 2-Phase Operation Reduces Input Capacitance 0.6V 1% Output Voltage Reference External Frequency Synchronization Monotonic Soft-Start Onboard High Current MOSFET Drivers Wide VIN Range: Up to 36V Adjustable Cycle-by-Cycle Current Limit Instant Output Overvoltage Protection Optional Short-Circuit Shutdown Timer Power Good Output with 100s Masking Available in 5mm x 5mm QFN Package
APPLICATIO S
s s s
Notebook and Palmtop Computers, PDAs Digital Signal Processors Network Servers
TYPICAL APPLICATIO
DB1
5V 10 1F 4.7F 100k DB2
CIN 10F 50V x4
VIN 3.3V TO 28V
VOUT1 2.5V 15A
L1 1.5H COUT1 + POSCAP 330F 4V x2 12.1k 19.1k D1 B340A
M1 CB1 0.22F
DRVCC PGOOD VCC TG1 TG2 BOOST2 BOOST1 SW1 SENSE1+ BG1 LTC3708 SW2 SENSE2+ BG2 SENSE2- PGND2 fIN
M2 CB2 0.22F
L2 1.2H D2 B340A
+
M3
M4 12.1k
SENSE1- PGND1
VOUT2 1.8V COUT2 15A POSCAP 470F 2.5V x2
VIN
RON1 1.5M 33k 10k 0.01F 180pF CSS 0.1F
6.04k
6.04k 0.01F
VFB1 VFB2 TRACK2 FCB ION1 ION2 ITH1 ITH2 INTLPF EXTLPF RUN/SS TRACK1 VRNG2 SGND VRNG1
VIN RON2 1M 1k 100k 33k 0.1F 5V 180pF
3708 F01
EFFICIENCY (%)
6.04k 0.01F
25k
L1, L2: PANASONIC ETQP3H M1, M2: RENESAS HAT2168 M3, M4: RENESAS HAT2165
Figure 1. High Efficiency Dual Output Step-Down Converter
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VOUT1 (0.5V/DIV) VOUT2 (0.5V/DIV)
2ms/DIV
100 95 90 85 80 75 70 0.01
3708 F01b
20VIN TO 2.5VOUT 5VIN TO 2.5VOUT 20VIN TO 1.8VOUT 5VIN TO 1.8VOUT 0.1 1 LOAD CURRENT (A) 10 15
3708 F01c
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LTC3708
ABSOLUTE
(Note 1)
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RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
Input Supply Voltage (VCC, DRVCC) ............ 7V to - 0.3V Boosted Topside Driver Supply Voltage (BOOST1, 2) ............................................. 42V to - 0.3V Switch Voltage (SW1, 2) ............................. 36V to - 5V SENSE1+, SENSE2+ Voltages ....................... 36V to - 5V SENSE1-, SENSE2- Voltages .................... 10V to -0.3V ION1, ION2 Voltages ................................... 21V to -0.3V (BOOST - SW) Voltages ..............................7V to - 0.3V RUN/SS, PGOOD Voltages .......................... 7V to - 0.3V PGOOD DC Current ................................................ 5mA TRACK1, TRACK2 Voltages ............ VCC + 0.3V to - 0.3V VRNG1, VRNG2 Voltages .................. VCC + 0.3V to - 0.3V ITH1, ITH2 Voltages ................................... 2.7V to - 0.3V VFB1, VFB2 Voltages.................................. 2.7V to - 0.3V INTLPF, EXTLPF Voltages ........................ 2.7V to - 0.3V FCB Voltages .............................................. 7V to - 0.3V Operating Temperature Range (Note 5) .. - 40C to 85C Junction Temperature (Note 2) ............................ 125C Storage Temperature Range ................ - 65C to 125C Reflow Peak Body Temperature ........................... 260C
32 31 30 29 28 27 26 25 RUN/SS 1 ITH1 2 VFB1 3 TRACK1 4 SGND 5 TRACK2 6 VFB2 7 ITH2 8 9 10 11 12 13 14 15 16 33 24 SENSE1- 23 PGND1 22 BG1 21 DRVCC 20 BG2 19 PGND2 18 SENSE2- 17 VCC
VRNG2
ION2
UH PACKAGE 32-LEAD (5mm x 5mm) PLASTIC QFN
EXPOSED PAD (PIN 33) IS SGND MUST BE SOLDERED TO PCB TJMAX = 125C, JA = 34C/ W
ORDER PART NUMBER UH PART MARKING
LTC3708EUH 3708
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Main Control Loop IQ Input DC Supply Current Normal Shutdown IFB1,2 Feedback Pin Input Current VREF Internal Reference Voltage VFB1,2 VFB(LINEREG)1,2 VFB(LOADREG)1,2 gm(EA)1,2 tON1,2 tON(MIN)1,2 tOFF(MIN)1,2 VSENSE(MAX)1,2 Feedback Voltage Feedback Voltage Line Regulation Feedback Voltage Load Regulation Error Amplifier Transconductance On-Time Minimum On-Time Minimum Off-Time Maximum Current Sense Threshold
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V, DRVCC = 5V, unless otherwise noted.
CONDITIONS MIN TYP MAX UNITS
VSENSE(MIN)1,2
Minimum Current Sense Threshold
ITH = 1.2V (Note 3) ITH = 1.2V, 0C to 85C (Notes 3, 4) ITH = 1.2V (Notes 3, 4) ITH = 1.2V (Note 3) VCC = 4.5V to 6.5V (Note 3) ITH = 0.5V to 1.9V (Note 3) ITH = 1.2V (Note 3) ION = 60A, VFCB = 0V ION = 30A, VFCB = 0V ION = 180A ION = 30A VRNG = 1V, VFB = 0.565V VRNG = 0V, VFB = 0.565V VRNG = VCC, VFB = 0.565V VRNG = 1V, VFB = 0.635V VRNG = 0V, VFB = 0.635V VRNG = VCC, VFB = 0.635V
q
0.594 0.591 0.594
q
1.2 94 186
125 90 180
2.4 250 - 50 0.600 0.600 0.600 0.02 - 0.05 1.45 116 233 50 270 143 100 200 - 62 - 42 - 88
SENSE2+
TG2
BOOST2
EXTLPF
INTLPF
SW2
SENSE1+
BOOST1
PGOOD
VRNG1
SW1
ION1
TG1
FCB
3 400 - 100 0.606 0.609 0.606 - 0.2 1.7 138 280 85 350 160 110 220
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mA A nA V V V %/V % mS ns ns ns ns mV mV mV mV mV mV
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LTC3708
ELECTRICAL CHARACTERISTICS
SYMBOL VFB(OV)1,2 VFB(UV)1,2 VRUN/SS(ON) VRUN/SS(LE) VRUN/SS(LT) IRUN/SS(C) IRUN/SS(D) VCC(UVLO) VCC(UVLOR) TG RUP1,2 TG RDOWN1,2 BG RUP1,2 BG RDOWN1,2 Tracking ITRACK1,2 VFB(TRACK1,2) TRACK Pin Input Current Feedback Voltage at Tracking PARAMETER Overvoltage Fault Threshold Undervoltage Fault Threshold RUN Pin Start Threshold RUN Pin Latchoff Enable Threshold RUN Pin Latchoff Threshold Soft-Start Charge Current Soft-Start Discharge Current Undervoltage Lockout Undervoltage Lockout Release TG Driver Pull-Up On-Resistance TG Driver Pull-Down On-Resistance BG Driver Pull-Up On-Resistance BG Driver Pull-Down On-Resistance
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V, DRVCC = 5V, unless otherwise noted.
CONDITIONS MIN 8.5 -380
q
TYP 10 -420 1.3 3 2.5 - 1.2 2 3.9 4.2 2 2 3 1 -100
MAX 11.5 -460 1.8 3.3 2.8 -2 3 4.2 4.4
UNITS % mV V V V A A V V
0.8 2.6 2.2 - 0.5 0.8
RUN/SS Pin Rising RUN/SS Pin Falling VRUN/SS = 0V VRUN/SS = VRUN/SS(LE), VFB1,2 = 0V VCC Falling VCC Rising TG High (Note 6) TG Low (Note 6) BG High (Note 6) BG Low (Note 6) ITH = 1.2V, VTRACK = 0.2V (Note 3) VTRACK = 0V, ITH = 1.2V (Note 3) VTRACK = 0.2V, ITH = 1.2V (Note 3) VTRACK = 0.4V, ITH = 1.2V (Note 3) Either VFB Rising Either VFB Falling VFB Returning IPGOOD = 5mA VPGOOD = 7V VFB Falling Measured with a DC Voltage at FCB Pin Measured with a AC Pulse at FCB Pin fFCB < fSW1, VEXTLPF = 0V fFCB > fSW1, VEXTLPF = 2.4 fSW1 < fSW2, VINTLPF = 0V fSW1 > fSW2, VINTLPF = 2.4 ION1 = 60A, VEXTPLL = 1.8V ION1 = 60A, VEXTPLL = 0.6V ION2 = 60A, VINTPLL = 1.8V ION2 = 60A, VINTPLL = 0.6V
-150 10 210 410 11.5 - 11.5 5 0.4 1
nA mV mV mV % % % V A s
-10 190 390 8.5 - 8.5
0 200 400 10 - 10 3 0.1
PGOOD Output VFBH1,2 VFBL1,2 VFB(HYS)1,2 VPGL IPGOOD PG Delay VFCB(DC) VFCB(AC) IEXTLPF PGOOD Upper Threshold PGOOD Lower Threshold PGOOD Hysteresis PGOOD Low Voltage PGOOD Leakage Current PGOOD Delay Forced Continuous Threshold Clock Input Threshold External Phase Detector Output Current Sourcing Capability Sinking Capability Internal Phase Detector Output Current Sourcing Capability Sinking Capability tON1 Modulation Range by External PLL Up Modulation Down Modulation tON2 Modulation Range by Internal PLL Up Modulation Down Modulation
100 1.9 1 2.1 1.5 20 -20 20 -20 186 233 58 233 58 2.3 2
Phase-Locked Loops V V A A A A ns ns ns ns
IINTLPF
tON(PLL)1
80
tON(PLL)2
186
80
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD as follows: LTC3708EUH: TJ = TA + (PD * 34C/W) Note 3: The LTC3708 is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (ITH).
Note 4: Internal reference voltage is tested indirectly by extracting error amplifier offset from the feedback voltage. Note 5: The LTC3708E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 6: RDS(ON) limit is guaranteed by design and/or correlation to static test.
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LTC3708
PI FU CTIO S
RUN/SS (Pin 1): Run Control and Soft-Start Input. A capacitor to ground at this pin sets the ramp rate of the output voltage (approximately 0.5s/F) and the time delay for overcurrent latchoff (see Applications Information). Forcing this pin below 0.8V shuts down the LTC3708. ITH1, ITH2 (Pins 2, 8): Error Amplifier Compensation Point and Current Control Threshold. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.8V corresponding to zero sense voltage (zero current). VFB1, VFB2 (Pins 3,7): Error Amplifier Feedback Input. This pin connects the error amplifier input to an external resistive divider from VOUT. Additional compensation can be implemented, if desired, using this pin. TRACK1, TRACK2 (Pins 4,6): Tie TRACK2 pin to a resistive divider connected to the output of channel 1 for either coincident or ratiometric output tracking. TRACK1 is used in the same manner between multiple LTC3708s (see Applications Information). To disable this feature, tie the pins to VCC. Do Not Float These Pins. SGND (Pins 5, 33): Signal Ground. All small-signal components and compensation components should connect to this ground and eventually connect to PGND at one point. The Exposed Pad must be soldered to the PCB. EXTLPF (Pin 9): Filter Connection for the External PLL. This PLL is used to synchronize the LTC3708 to an external clock. INTLPF (Pin 10): Filter Connection for the Internal PLL. This PLL is used to phase shift the second channel to the first channel by 180. VCC (Pin 17): Main Input Supply. Decouple this pin to SGND with an RC filter (10, 1F for example). DRVCC (Pin 21): Driver Supply. Provides supply to the drivers for the bottom gates. Also used for charging the bootstrap capacitors. BG1, BG2 (Pins 22,20): Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFET between ground and DRVCC. PGND1, PGND2 (Pins 23,19): Power Ground. Connect this pin closely to the source of the bottom N-channel MOSFET, the (-) terminal of CDRVCC and the (-) terminal of CIN. SENSE1-, SENSE2- (Pins 24,18): Current Sense Comparator Input. The (-) input to the current comparator is used to accurately Kelvin sense the bottom side of the sense resistor or MOSFET. SENSE1+, SENSE2+ (Pins 25,16): Current Sense Comparator Input. The (+) input to the current comparator is normally connected to the SW node unless using a sense resistor (See Applications Information). SW1, SW2 (Pins 26,15): Switch Node. The (-) terminal of the bootstrap capacitor CB connects here. This pin swings from a Schottky diode voltage drop below ground up to VIN. TG1, TG2 (Pins 27,14): Top Gate Drive. Drives the top Nchannel MOSFET with a voltage swing equal to DRVCC superimposed on the switch node voltage SW. BOOST1, BOOST2 (Pins 28,13): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor CB connects here. This pin swings from a diode voltage drop below DRVCC up to VIN + DRVCC. ION1, ION2 (Pins 29,12): On-Time Current Input. Tie a resistor from VIN to this pin to set the one-shot timer current and thereby set the switching frequency. PGOOD (Pin 30): Power Good Output. Open-drain logic output that is pulled to ground when either or both output voltages are not within 10% of the regulation point. The output voltage must be out of regulation for at least 100s before the power good output is pulled to ground. FCB (Pin 31): Forced Continuous and External Clock Input. Tie this pin to ground to force continuous synchronous operation or to VCC to enable discontinuous mode operation at light load. Feeding an external clock signal into this pin will synchronize the LTC3708 to the external clock and enable forced continuous mode. VRNG1, VRNG2 (Pins 32,11): Sense Voltage Range Input. The voltage at this pin is ten times the nominal sense voltage at maximum output current and can be programmed from 0.5V to 2V. The sense voltage defaults to 70mV when this pin is tied to ground, 140mV when tied to VCC.
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LTC3708
FU CTIO AL DIAGRA
FCB CLOCK DETECTOR FROM CHANNEL 2 TG EXTLPF ENABLE PHASE DETECTOR (PD2) PHASE DETECTOR (PD1)
OST tON = 0.7 (10pF) IION
R Q S 20k
+
ICMP
-
1.4V VRNG
x
0.7V OV
3.3A
1 240k ITH
EA
Q4
UV
RC VREFB TRACK Q1 Q2 Q3
DUPLICATE FOR SECOND CHANNEL CONTROLLER
-+
1.3V RUN/SS CSS
3708 FD
+ -
VREF 0.6V
1.3V RUN SHDN 1.2A 6V
+
CC1
-
-
+
-
+
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INTLPF ION RON VCC
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CIN CVCC
VIN
0.6V REF
TO CHANNEL 2 OST FCNT ON
BOOST TG SW L1 SWITCH LOGIC SENSE+ DRVCC SHDN OV BG PGND SENSE- CDRVCC M2 DB VOUT CB M1
+
IREV
+
COUT
-
0.66V VFB R2
SGND
R1
0.54V PGOOD ENABLE >100s BLANKING FROM CHANNEL 2 OV AND UV COMPARATORS
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LTC3708
OPERATIO
Main Control Loop The LTC3708 uses a constant on-time, current mode stepdown architecture with two control channels operating at 180 degrees out of phase. In normal operation, each top MOSFET is turned on for a fixed interval determined by its own one-shot timer OST. When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and repeating the cycle. The trip level of the current comparator is set by the ITH voltage which is the output of each error amplifier EA. Inductor current is determined by sensing the voltage between the SENSE- and SENSE+ pins using either the bottom MOSFET on-resistance or a separate sense resistor. At low load currents, the inductor current can drop to zero and become negative. This is detected by current reversal comparator IREV, which then shuts off M2 resulting in discontinuous operation. Both switches will remain off with the output capacitor supplying the load current until the ITH voltage rises above the zero current level (0.8V) to initiate another cycle. Discontinuous mode operation is disabled when the FCB pin is brought below 1.9V, forcing continuous synchronous operation. The main control loop is shut down by pulling the RUN/SS pin low, turning off both M1 and M2. Releasing the pin allows an internal 1.2A current source to charge an external soft-start capacitor CSS. When this voltage reaches 1.3V, the controller turns on and begins switching, but with the effective reference voltage clamped at 0V. As CSS continues to charge, the effective reference ramps up at the same rate and controls the rise rate of the output voltage. Operating Frequency The operating frequency is determined implicitly by the top MOSFET on-time and the duty cycle required to maintain regulation. The one-shot timer generates an ontime that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in VIN. The nominal frequency can be adjusted with an
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(Refer to Functional Diagram)
external resistor RON. When the LTC3708 is synchronized to an external clock, the operating frequency will then be solely determined by the external clock. Output Overvoltage Protection An overvoltage comparator OV guards against transient overshoots (>10%) as well as other more serious conditions that may overvoltage the output. In this condition, M1 is turned off and M2 is turned on and held on until the condition is cleared. Short-Circuit Detection and Protection After the controller has been started and given adequate time to charge the output capacitors, the RUN/SS capacitor is used as the short-circuit time-out capacitor. If either one of the output voltages falls to less than 70% of its nominal output voltage, the RUN/SS capacitor begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. If the condition lasts for a long enough period, as determined by the size of the RUN/SS capacitor, both controllers will be shut down until the RUN/SS pin voltage is recycled. This builtin latchoff can be overridden by providing >5A pull-up at a compliance of 5V to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor during an overcurrent and/or short-circuit condition. Power Good (PGOOD) Pin Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage exceeds a 10% window around the regulation point. In addition, the output feedback voltage must be out of this window for a continuous duration of at least 100s before PGOOD is pulled low. This is to prevent any glitch on the feedback voltage from creating a false power bad signal. The PGOOD will indicate high immediately when the feedback voltage is in regulation.
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LTC3708
OPERATIO
DRVCC
Power for the top and bottom MOSFET drivers is derived from the DRVCC pin. The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is normally recharged from DRVCC through an external Schottky diode DB when the top MOSFET is turned off. 2-Phase Operation For the LTC3708 to operate optimally as a 2-phase controller, the resistors connected to the ION pins must be selected such that the free-running frequency of each channel is close to that of the other. An internal phaselocked loop (PLL) will then ensure that channel 2 operates at the same frequency as channel 1, but phase shifted by 180. The loop filter connected to the INTLPF pin provides stability to the PLL. For external clock synchronization, a second PLL is incorporated to adjust the on-time of channel 1 until its frequency is the same as the external clock. Compensation for the external PLL is through the EXTLPF pin. The LTC3708's 2-phase operation brings considerable benefits to portable applications and automatic electronics. It lowers the input filtering requirement, reduces electromagnetic interference (EMI) and increases the power conversion efficiency. Until the introduction of the 2-phase operation, dual switching regulators operated both channels in phase (i.e., single phase operation). This means that both controlling switches turned on at the same time, causing current pulses of up to twice the amplitude of
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(Refer to Functional Diagram)
those for one regulator to be drawn from the input capacitor or battery. Such operation results in higher input RMS current, larger and/or more expensive input capacitors, more power loss and worse EMI in the input source (whether a wall adapter or a battery). In contrast to single phase operation, the two channels of a 2-phase switching regulator are operated 180 degrees out of phase. This effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together. The result is a significant reduction in total RMS input current, which in turn allows less expensive input capacitors to be used, reduces shielding requirements for EMI and improves real world operating efficiency. Figure 2 compares the input waveforms for a representative single phase dual switching regulator to the 2-phase dual switching regulator. An actual measurement of the RMS input current under these conditions shows that 2-phase dropped the input current from 2.53ARMS to 1.55ARMS. While this is an impressive reduction in itself, remember that the power losses are proportional to I2RMS, meaning that the actual power wasted is reduced by a factor of 2.66. The reduced input ripple current also means that less power is lost in the input power path, which could include batteries, switches, trace/connector resistances and protection circuitry. Improvements in both conducted and radiated EMI also directly accrue as a result of the reduced RMS input current and voltage.
5V SWITCH 20V/DIV 3.3V SWITCH 20V/DIV INPUT CURRENT 5A/DIV INPUT VOLTAGE 500mV/DIV
IIN(MEAS) = 2.53ARMS
3708 F02a
IIN(MEAS) = 1.55ARMS
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(2a)
(2b)
Figure 2. Input Waveforms Comparing Single Phase (2a) and 2-Phase (2b) Operation for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each
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LTC3708
OPERATIO
INPUT RMS CURRENT (A)
Of course, the improvement afforded by 2-phase operation is a function of the dual switching regulator's relative duty cycles which, in turn, are dependent upon the input voltage, VIN. Figure 3 shows how the RMS input current varies for single phase and 2-phase operation for 3.3V and 5V regulators over a wide input voltage range. It can readily be seen that the advantages of 2-phase operation are not just limited to a narrow operating range, but in fact extend over a wide region. A good rule of thumb for most applications is that 2-phase operation will reduce the input capacitance requirement to that for just one channel operating at maximum current and 50% duty cycle.
APPLICATIO S I FOR ATIO
The basic LTC3708 application circuit is shown in Figure 1. External component selection is primarily determined by the maximum load current and begins with the selection of the power MOSFET switches and/or sense resistor. For the LTC3708, the inductor current is determined by the RDS(ON) of the synchronous MOSFET or by a sense resistor when the user opts for more accurate current sensing. The desired amount of ripple current and operating frequency largely determines the inductor value. Finally, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple specification. Maximum Sense Voltage and VRNG Pin Inductor current is determined by measuring the voltage across the RDS(ON) of the synchronous MOSFET or through a sense resistor that appears between the SENSE+ and SENSE- pins. The maximum sense voltage is set by the voltage applied to the VRNG pin and is equal to approximately VRNG /7. The current mode control loop will not allow the inductor current valleys to exceed VRNG /(7 * RSENSE). In practice, one should allow some margin for variations in the LTC3708 and external component values. A good guide for selecting the sense resistance is:
RSENSE = VRNG 10 * IOUT (MAX)
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(Refer to Functional Diagram)
3.0 2.5 2.0 1.5 1.0 0.5 0 2-PHASE DUAL CONTROLLER SINGLE PHASE DUAL CONTROLLER
VO1 = 5V/3A VO2 = 3.3V/3A 0 10 20 30 INPUT VOLTAGE (V) 40
3708 F03
Figure 3. RMS Input Current Comparison
The voltage of the VRNG pin can be set using an external resistive divider from VCC between 0.5V and 2V, resulting in nominal sense voltages of 50mV to 200mV. Additionally, the VRNG pin can be tied to ground or VCC, in which case the nominal sense voltage defaults to 70mV or 140mV, respectively. The maximum allowed sense voltage is about 1.4 times this nominal value. Connecting the SENSE+ and SENSE - Pins The LTC3708 provides the user with an optional method to sense current through a sense resistor instead of using the RDS(ON) of the synchronous MOSFET. When using a sense resistor, it is placed between the source of the synchronous MOSFET and ground. To measure the voltage across this resistor, connect the SENSE+ pin to the source of the synchronous MOSFET and the SENSE- pin to the other end of the resistor. The SENSE+ and SENSE- pins provide the Kelvin connections, ensuring accurate voltage measurement across the resistor. Using a sense resistor provides a well-defined current limit, but adds cost and reduces efficiency. Alternatively, one can use the synchronous MOSFET as the current sense element by simply connecting the SENSE+ pin to the switch node SW and the SENSE- pin to the source of the synchronous MOSFET, eliminating the sense resistor. This improves efficiency, but one must carefully choose the MOSFET on-resistance as discussed below.
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LTC3708
APPLICATIO S I FOR ATIO
Power MOSFET Selection
Each output stage of the LTC3708 requires two external N-channel power MOSFETs, one for the top (main) switch and one for the bottom (synchronous) switch. Important parameters for the power MOSFETs are the breakdown voltage V(BR)DSS, threshold voltage VGS(TH), on-resistance RDS(ON), reverse transfer capacitance CRSS and maximum current IDS(MAX). The gate drive voltage is set by the 5V DRVCC supply. Consequently, logic-level threshold MOSFETs must be used in LTC3708 applications. If the driver's voltage is expected to drop below 5V, then sub-logic level threshold MOSFETs should be considered. When the bottom MOSFET is used as the current sense element, particular attention must be paid to its onresistance. MOSFET on-resistance is typically specified with a maximum value RDS(ON)(MAX) at 25C. Additional margin is required to accommodate the rise in MOSFET on-resistance with temperature:
RDS(ON)(MAX) =
RSENSE T
The T term is a normalization factor (unity at 25C) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/C. For a maximum junction temperature of 100C, using a value 100C = 1.3 is reasonable (see Figure 4).
2.0
T NORMALIZED ON-RESISTANCE
1.5
1.0
0.5
0 - 50
50 100 0 JUNCTION TEMPERATURE (C)
150
3708 F04
Figure 4. RDS(ON) vs Temperature
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The power dissipated by the top and bottom MOSFETs strongly depends upon their respective duty cycles and the load current. When the LTC3708 is operating in continuous mode, the duty cycles for the MOSFETs are:
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D TOP = DBOT
VOUT VIN V -V = IN OUT VIN
The resulting power dissipation in the MOSFETs at maximum output current are:
PTOP = DTOP * IOUT(MAX)2 * T(TOP) * RDS(ON) + (0.5) * VIN2 * IOUT(MAX) * CRSS * f * 1 1 RDR * + VGS(TH) DRVCC - VGS(TH)
(
)
PBOT = DBOT * IOUT(MAX)2 * T(BOT) * RDS(ON)
Both MOSFETs have I2R losses and the top MOSFET includes an additional term for transition losses, which are largest at high input voltages. The bottom MOSFET losses are greatest when the bottom duty cycle is near 100%, during a short circuit or at high input voltage. Operating Frequency The choice of operating frequency is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching and driving losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. The operating frequency of LTC3708 applications is determined implicitly by the one-shot timer that controls the on time, tON, of the top MOSFET switch. The on time is set by the current into the ION pin according to:
tON = 0.7 (10pF ) IION
Tying a resistor, RON, from VIN to the ION pin yields an on time inversely proportional to VIN. For a step-down
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LTC3708
APPLICATIO S I FOR ATIO
converter, this results in approximately constant frequency operation as the input supply varies:
f= VOUT 0.7 * RON (10pF )
Figure 5 shows how RON relates to switching frequency for several common output voltages.
1000
SWITCHING FREQUENCY (kHz)
VOUT = 3.3V VOUT = 1.5V VOUT = 2.5V
100 100
1000 RON (k)
10000
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Figure 5. Switching Frequency vs RON
PLL and Frequency Synchronization In the LTC3708, there are two onboard phase-locked loops (PLL). One PLL is used to achieve frequency locking and 180 phase shift between the two channels while the second PLL locks onto the rising edge of an external clock. Since the LTC3708 uses a constant on-time architecture, the error signal generated by the phase detector of the PLL is used to vary the on time to achieve frequency locking and phase separation. The variable on-time range is from 0.5 * tON to 2 * tON, where tON is the initial on time set by the RON resistor. To fully utilize the frequency synchronization range of the PLL, it is advisable to set the initial on time properly so that the two channels have close free-running frequencies. Frequencies far apart may exceed the synchronization capability of the PLL. If the two output voltages are VOUT1 and VOUT2, for example, RON resistors should then be selected proportionally:
RON1 VOUT1 = RON2 VOUT2
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Similarly, if the external PLL is engaged to synchronize to an external frequency of fEXT, RON1 should be selected close to:
RON1 = VOUT1 0.7 * fEXT * 10pF VOUT2 hence, RON2 = 0.7 * fEXT * 10pF
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In this case, channel 1 will first be synchronized to the external frequency and channel 2 will then be synchronized to channel 1 with 180 phase separation. Inductor Selection Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current:
V V IL = OUT 1 - OUT f *L VIN
Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and ripples in the output voltage. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a trade-off between component size and efficiency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to:
VOUT VOUT L= 1- V f * IL(MAX) IN(MAX)
Once the value for L is known, the type of inductor must be selected. A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida and Panasonic. Schottky Diodes D1 and D2 Selection The Schottky diodes D1 and D2 shown in Figure 1 conduct during the dead time between the conduction of the power MOSFET switches. They are intended to prevent the body
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diode of the bottom MOSFET from turning on and storing charge during the dead time, which causes a modest (about 1%) efficiency loss. The diodes can be rated for about one-half to one-fifth of the full load current since they are on for only a fraction of the duty cycle. In order for the diodes to be effective, the inductance between them and the bottom MOSFETs must be as small as possible, mandating that these components be placed as close as possible in the circuit board layout. The diodes can be omitted if the efficiency loss is tolerable. CIN and COUT Selection The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst case RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used in the formula below to determine the maximum RMS current requirement. Increasing the output current, drawn from the other out-of-phase controller, will actually decrease the input RMS ripple current from this maximum value (see Figure 3). The type of input capacitor, value and ESR rating have efficiency effects that need to be considered in the selection process. The capacitance value chosen should be sufficient to store adequate charge to keep pulsating input currents down. 20F to 40F is usually sufficient for a 25W output supply operating at 200kHz. The ESR of the capacitor is important for capacitor power dissipation as well as overall efficiency. All of the power (RMS ripple current2 * ESR) not only heats up the capacitor but wastes power from the battery. Medium voltage (20V to 35V) ceramic, tantalum, OS-CON and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramic voltage coefficients are very high and may have audible piezoelectric effects; tantalums need to be surge-rated; OS-CONs suffer from higher inductance, larger case size and limited surface-mount applicability; electrolytics' higher ESR and dryout possibility require several to be used. 2-phase systems allow the lowest amount of capacitance overall. As little as one 22F or two to three
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10F ceramic capacitors are an ideal choice in a 20W to 35W power supply due to their extremely low ESR. Even though the capacitance at 20V is substantially below their rating at zero-bias, very low ESR loss makes ceramics an ideal candidate for highest efficiency battery operated systems. Also consider parallel ceramic and high quality electrolytic capacitors as an effective means of achieving ESR and bulk capacitance goals. In continuous mode, the current of the top N-channel MOSFET is approximately a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by:
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[VOUT (VIN - VOUT )]1/2 IRMS IMAX
VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. The benefit of the LTC3708 2-phase operation can be calculated by using the equation above for the higher power channel and then calculating the loss that would have resulted if both controller channels switch on at the same time. The total RMS power lost is lower when both controllers are operating due to the interleaving of current pulses through the input capacitor's ESR. This is why the input capacitor's requirement calculated above for the worst-case controller is adequate for the dual controller design. Remember that input protection fuse resistance, battery resistance and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. The overall benefit of a 2-phase design will only be fully realized when the source impedance of
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the power supply/battery is included in the efficiency testing. The drains of the two top MOSFETS should be placed within 1cm of each other and share a common CIN(s). Separating the drains and CIN may produce undesirable voltage and current resonances at VIN.
The selection of COUT is driven by the effective series resistance (ESR) required to minimize voltage ripple and load step transients. The output ripple (VOUT) is determined by:
1 VOUT IL ESR + 8fC OUT
where f = operating frequency, COUT = output capacitance, and IL= ripple current in the inductor. The output ripple is highest at maximum input voltage since IL increases with input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Manufacturers such as Nichicon, United Chemi-Con and Sanyo can be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to reduce the inductance effects. In surface mount applications multiple capacitors may need to be used in parallel to meet the ESR, RMS current handling and load step requirements of the application. Aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. Special polymer capacitors offer very low ESR but have lower storage capacity per unit volume than other capacitor types. These capacitors offer a very cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. Tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. Several excellent surge-tested choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors can be used in cost-driven applications providing that
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consideration is given to ripple current ratings, temperature and long term reliability. A typical application will require several to many aluminum electrolytic capacitors in parallel. A combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. Other capacitor types include Nichicon PL series, Sanyo POSCAP, NEC Neocap, Cornell Dubilier ESRE and Sprague 595D series. Consult manufacturers for other specific recommendations. Top MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from DRVCC when the switch node is low. Note that the average voltage across CB is approximately DRVCC. When the top MOSFET turns on, the switch node rises to VIN and the BOOST pin rises to approximately VIN + DRVCC. The boost capacitor needs to store about 100 times the gate charge required by the top MOSFET. In most applications 0.1F to 0.47F is adequate. Discontinuous Mode Operation and FCB Pin The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin above its 2.3V threshold (typically to VCC) enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. The load current at which current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current and the ripple current depends on the choice of inductor value and operating frequency as well as the input and output voltages. Tying the FCB pin below 1.9V forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. Besides providing a logic input to force continuous operation, the FCB pin acts as the input for external clock synchronization. Upon detecting the presence of an external clock signal, channel 1 will lock on to this external clock and this will be followed by channel 2 (see PLL and Frequency Synchronization). The LTC3708 defaults to forced continuous mode when sychronized to an external clock.
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Fault Conditions: Current Limit
The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LTC3708, the maximum sense voltage is controlled by the voltage on the VRNG pin. With valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is:
ILIMIT =
SWITCHING FREQUENCY (MHz)
VSNS(MAX) 1 + * IL RDS(ON) * T 2
The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit generally occurs with the largest VIN at the highest ambient temperature, conditions which cause the largest power loss in the converter. Note that it is important to check for self-consistency between the assumed junction temperature and the resulting value of ILIMIT, which heats the junction. Caution should be used when setting the current limit based upon the RDS(ON) of the MOSFETs. The maximum current limit is determined by the minimum MOSFET on-resistance. Data sheets typically specify nominal and maximum values for RDS(ON), but not a minimum. A reasonable assumption is that the minimum RDS(ON) lies the same amount below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines. For a more accurate current limiting, a sense resistor can be used. Sense resistors in the 1W power range can be easily available in the 5%, 2% or 1% tolerance. The temperature coefficient of these resistors is very low, ranging from 250ppm/C to 75ppm/C. In this case, the (RDS(ON) * T) product in the above equation can simply be replaced by the RSENSE value. Minimum Off Time and Dropout Operation The minimum off time tOFF(MIN) is the smallest amount of time that the LTC3708 is capable of turning on the bottom MOSFET, tripping the current comparator and turning the MOSFET back off. This time is generally about 270ns. The minimum off time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached,
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due to a dropping input voltage for example, then the output will drop out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT tON + tOFF(MIN) tON A plot of maximum frequency vs duty cycle is shown in Figure 6.
2.0 1.5 DROPOUT REGION 1.0 0.5 0 0 0.25 0.50 0.75 DUTY CYCLE (VOUT/VIN) 1.0
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Figure 6. Maximum Switching Frequency vs Duty Cycle
Soft-Start and Latchoff with the RUN/SS Pin The RUN/SS pin provides a means to shut down the LTC3708 as well as a timer for soft-start and overcurrent latchoff. Pulling the RUN/SS pin below 0.8V shuts down the LTC3708. Releasing the pin allows an internal 1.2A internal current source to charge the external capacitor CSS. If RUN/SS has been pulled all the way to ground, there is a delay before starting of about:
tDELAY =
1.3V * CSS = (1.1s / F )CSS 1.2A
When the RUN/SS voltage reaches the ON threshold (typically 1.3V), the LTC3708 begins operating with a clamp on channel 1's reference voltage. The clamp level is one threshold voltage below RUN/SS. As the voltage on RUN/SS continues to rise, channel 1's reference is raised at the same rate, achieving monotonic output voltage soft-start (Figure 7). When RUN/SS rises 0.6V above the
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RUN/SS V = 0.6V ON THRESHOLD TIME VOUT1
TIME
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Figure 7. Monotonic Soft-Start Waveforms
ON threshold, the reference clamp is invalidated and the internal precision reference takes over. When channel 2 is tracked to channel 1, soft-start on channel 2 is automatically achieved (see Output Voltage Tracking). Controlled soft-start requires that the timing capacitor, CSS, be made large enough to guarantee that the output can track the voltage rise on the RUN/SS pin. The minimum CSS capacitance can be calculated:
R1 + R2 30A * RSENSE CSS > * * COUT R1 VRNG
where R1 and R2 are the feedback resistive dividers (Functional Diagram), COUT is the output capacitance and RSENSE is the current sense resistance. When bottom MOSFET RDS(ON) is used for current sensing, RSENSE should be replaced with the worst-case RDS(ON)(MAX). Generally, 0.1F is more than sufficient for CSS. After the controller has been started and given adequate time to charge the output capacitor, CSS is used as a shortcircuit timer. After the RUN/SS pin charges above 3V and if either output voltage falls below 70% of its regulated value, a short-circuit fault is assumed. A 2A current then begins discharging CSS. If the fault condition persists until the RUN/SS pin drops to 2.5V, the controller turns off all power MOSFETs, shutting down both channels. The RUN/SS pin must be actively pulled down to ground in order to restart operation.
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Overcurrent latchoff operation is not always needed or desired and can prove annoying during troubleshooting. This feature can be overridden by adding a pull-up current of >5A to the RUN/SS pin (Figure 8). The additional current prevents the discharge of CSS during a fault and also shortens the soft-start period.
VIN 3.3V OR 5V D1 RUN/SS RSS* CSS
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*OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF
Figure 8. RUN/SS Pin Interfacing with Latchoff Defeated
Output Voltage Tracking The LTC3708 allows the user to program how the second channel output ramps up and down by means of the TRACK2 pin. Through this pin, the second channel output can be set up to either coincidently or ratiometrically track the channel 1 output, as shown in Figure 9. Similar to RUN/SS, the TRACK2 pin acts as a clamp on channel 2's reference voltage. VOUT2 is referenced to the TRACK2 voltage when the TRACK2 < 0.6V and to the internal precision reference when TRACK2 > 0.6V. To implement the tracking in Figure 9a, connect an extra resistive divider to the output of channel 1 and connect its midpoint to the TRACK2 pin. The ratio of this divider should be selected the same as that of channel 2's feedback divider (Figure 10a). In this tracking mode, VOUT1 must be set higher than VOUT2. To implement the ratiometric tracking in Figure 9b, no extra divider is needed; simply connect the TRACK2 pin to the VFB1 pin (Figure 10b). By selecting different resistors, the LTC3708 can achieve different modes of tracking including the two in Figure 9. So which mode should be programmed? While either mode in Figure 9 satisfies most practical applications, there does exist some tradeoff. The ratiometric mode saves a pair of resistors but the coincident mode offers better output regulation. This can be better understood
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OUTPUT VOLTAGE
VOUT2
OUTPUT VOLTAGE
TIME
(9a) Coincident Tracking
Figure 9. Two Different Modes of Output Voltage Tracking
VOUT1 R3 TO TRACK2 PIN R4 R2 R1 TO VFB1 PIN TO VFB2 PIN R4 R3 TO TRACK2 PIN R2 VOUT2 VOUT1 R1 TO VFB1 PIN TO VFB2 PIN R4
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(10a) Coincident Tracking Setup
Figure 10. Setup for Coincident and Ratiometric Tracking
R3 VOUT2 R1 VOUT1 = - 1, = - 1 R2 0.6 R4 0.6
I
I
+
D1 TRACK2 0.6V VFB2 D3
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D2
EA2
-
Figure 11. Equivalent Input Circuit of Error Amplifier of Channel 2
with the help of Figure 11. At the input stage of channel 2's error amplifier, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. The top two current sources are of the same amplitude. In the coincident mode, the TRACK2 voltage is substantially higher than 0.6V at steady state and effectively turns off D1. D2 and D3 will therefore conduct the same current
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VOUT1 VOUT1 VOUT2 TIME
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(9b) Ratiometric Tracking
VOUT2 R3
(10b) Ratiometric Tracking Setup
and offer tight matching between VFB2 and the internal precision 0.6V reference. In the ratiometric mode, however, TRACK2 equals 0.6V even at steady state. D1 will divert part of the bias current and make VFB2 slightly lower than 0.6V. Although this error is minimized by the exponential I-V characteristic of the diodes, it does impose a finite amount of output voltage deviation. Further, when channel 1's output experiences dynamic excursions (under load transient, for example), channel 2 will be affected as well. For better output regulation, use the coincident tracking mode instead of ratiometric. The number of resistors in Figure 10a can be further reduced with the scheme in Figure 12. In a system that requires more than two tracked supplies, multiple LTC3708s can be daisy-chained through the TRACK1 pin. TRACK1 clamps channel 1's reference in the same manner TRACK2 clamps channel 2. To eliminate the
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possibility of multiple LTC3708s coming on at different times, only the master LTC3708's RUN/SS pin should be connected to a soft-start capacitor. All other LTC3708s should have their RUN/SS pins connected to VCC. Figure 13 shows the circuit with four outputs. Three of them are programmed in the coincident mode while the fourth one tracks ratiometrically. If output tracking is not needed, connect the TRACK pins to VCC. Do Not Float These Pins.
VOUT1 R1 TO TRACK2 PIN R2 TO VFB1 PIN R3 R5 R4 TO VFB2 PIN VOUT2
Figure 12. Alternative Setup for Coincident Tracking
R1 R4 VOUT2 R1 + R2 VOUT1 = - 1, = = - 1 R3 0.6 R2 + R3 R5 0.6
TO VCC VOUT1 R4 R5 R1
TRACK1 TRACK2 LTC3708 "MASTER" VFB1 VFB2
CSS
OUTPUT VOLTAGE
R2
R2
R2
RUN/SS
TRACK1 TRACK2 VOUT3 R4 LTC3708 "SLAVE" VFB1 R2 TO VCC RUN/SS VFB2
(13a) Circuit Setup
Figure 13. Four Outputs with Tracking and Ratiometric Sequencing
R3 VOUT2 R4 VOUT3 R5 VOUT4 R1 VOUT1 = - 1, = - 1, = - 1, = - 1 R2 0.6 0.6 0.6 0.6 R2 R2 R2
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Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3708 circuits: 1. DC I2R Losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode, the average output current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss. For example, if RDS(ON) = 0.01 and RL = 0.005, the loss will range from 15mW up to 1.5W as the output current varies from 1A to 10A.
VOUT2 R3 VOUT1 R2 VOUT3 VOUT4 R5 VOUT4 VOUT2 R2 TIME
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(13b) Output Voltage
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2. Transition Loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated from:
Transition Loss (0.5) * VIN2 * IOUT * CRSS * f * 1 1 RDS(ON)_ DRV + DRVCC - VGS(TH) VGS(TH)
3. DRVCC and VCC Current. This is the sum of the MOSFET driver and control currents. The driver current supplies the gate charge QG required to switch the power MOSFETs. This current is typically much larger than the control circuit current. In continuous mode operation: IGATECHG = f(QG(TOP) + QG(BOT)) 4. CIN Loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. The LTC3708 2-phase architecture typically halves this CIN loss over the single phase solutions. Other losses, including COUT ESR loss, Schottky conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. When making any adjustments to improve efficiency, the final arbiter is the total input current for the regulator at your operating point. If you make a change and the input current decreases, then you improve the efficiency. If there is no change in input current, then there is no change in efficiency. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When
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a load step occurs, VOUT immediately shifts by an amount equal to ILOAD (ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problems. The ITH pin external components shown in Figure 1 will provide adequate compensation for most applications. For a detailed explanation of switching control loop theory see Linear Technology Application Note 76. Design Example As a design example, take a supply with the following specifications: VIN = 7V to 28V (15V nominal), VOUT1 = 2.5V, VOUT2 = 1.8V, IOUT1(MAX) = IOUT2(MAX) = 10A, f = 500kHz and VOUT2 to track VOUT1. First calculate the timing resistor:
RON1 = 2.5V = 714k (0.7V)(500kHz)(10pF )
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Select a standard value of 715k.
RON2 =
1.8 V = 514k (0.7V)(500kHz)(10pF)
Select a standard value of 511k. Next, choose the feedback resistors: R1 2.5V = - 1 = 3.17 R2 0.6 V Select R1 = 31.6k, R2 = 10k. R3 1.8 V = - 1= 2 R4 0.6 V Select R3 = 20k, R4 = 10k. For VOUT2 to coincidently track VOUT1 at start-up, connect an extra pair of R3 and R4 across VOUT1 with its midpoint tied to the TRACK2 pin.
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Third, design the inductors for about 40% ripple current at the maximum VIN:
L1 = 2.5V 2.5V 1- = 1.1H (500kHz)(0.4)(10A) 28V
A standard 1H inductor will result in 41% of ripple current (4.1A) at worst case.
L2 = 1.8 V 1.8 V 1- = 0.8 H (500kHz)(0.4)(10A) 28V
L2 can also use 1H to save some BOM (Bill of Material) cost; the resulting ripple current is 3.4A. The selection of MOSFETs is simplified by the fact that both channels have the same maximum output current. Select the top and bottom MOSFETs for one channel and the same MOSFETs can be used for the other. Take channel 1 for calculation and begin with the bottom synchronous MOSFET. As stated previously in the Power MOSFET Selection section, the major criterion in selecting the bottom MOSFET is low RDS(ON). Choose an Si4874 for example: RDS(ON) = 0.0083 (nom) 0.010 (max), JA = 40C/W. The nominal sense voltage is: VSNS(NOM) = (10A)(1.3)(0.0083) = 108mV Tying VRNG1 to 1.1V will set the current sense voltage range for a nominal value of 110mV with the current limit occurring at 146mV. To check if the current limit is acceptable, assume a junction temperature of about 80C above a 70C ambient with 150C = 1.5:
146mV 1 ILIMIT + (4.1A ) = 11.8 A (1.5)(0.010) 2
and double check the assumed TJ in the MOSFET: PBOT = 28 V - 2.5V (11.8A)2 (1.5)(0.010) = 1.9W 28 V
TJ = 70C + (1.90W)(40C/W) = 146
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Because the top MOSFET is on for only a short time, an Si4884 will be sufficient: RDS(ON) = 0.0165 (max), CRSS = 190pF, VGS(TH) = 1V, JA = 42C/W. Checking its power dissipation at current limit with 130C = 1.6:
PTOP = 2.5V (11.8A)2 (1.6)(0.0165) + (0.5)(28V)2 28 V (11.8A)(190pF )(500kHz)(2) 5V 1 1V + 11 - V = 0.33W + 1.10W = 1.43W
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TJ = 70C + (1.43W)(42C/W) = 130 The junction temperatures for both top and bottom MOSFETs will be significantly less at nominal current, but the above analysis shows that careful attention to PCB layout and heat sinking will be necessary in this circuit. The same MOSFETs (Si4874 and Si4884) can be used for channel 2. Finally, an input capacitor is chosen for an RMS current rating of about 5A at 85C and the output capacitors are chosen for a low ESR of 0.013 to minimize output voltage changes due to inductor ripple current and load steps. The ripple voltage will be only: VOUT1(RIPPLE) = IL1(ESR) = (4.1A)(0.013) = 52mV VOUT2(RIPPLE) = IL2(ESR) = (3.4A)(0.013) = 44mV However, a 0A to 10A load step will cause an output change of up to: VOUT(STEP) = ILOAD(ESR) = (10A)(0.013) = 130mV An optional 22F ceramic output capacitor is included to minimize the effect of ESL in the output ripple. The complete circuit is shown in Figure 14.
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VIN 7V TO 28V CIN 10F 35V x4 BAT54A
BOOST2 VCC 17 4 31 21 VCC TRACK1 FCB DRVCC 27 TG1 TG2 28 BOOST1 BOOST2 0.22F 26 SW1 SW2 25 SENSE2+ SENSE1+ 22 LTC3708 BG2 BG1 24 - SENSE2- SENSE1 23 PGND1 PGND2 32 VRNG1 VRNG2 VRNG2 29 ION1 ION2 3 VFB2 VFB1 6 TRACK2 PWRGD 9 EXTLPF INTLPF 0.01F 2 ITH1 ITH2 1F RUN/SS 100pF 20k 680pF CIN: UNITED CHEMI-CON THCR60EIH106ZT COUT1, COUT2: SANYO POSCAP 4TPD470M L1, L2: SUMIDA CEP125-1R0M M1, M2: VISHAY Si4884 M3, M4: VISHAY Si4874 1 0.1F SGND 5
VOUT1 2.5V 10A 22F 6.3V X7R
L1 1H
M1
+
COUT1 470F 4V
D1 B340A
M3
20k 1% 56pF
R1 31.6k 1% VIN
714k
10k 1%
R2 10k 1%
Figure 14. Design Example: 2.5V/10A and 1.8V/10A at 500kHz with Output Tracking
PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3708. These items are also illustrated graphically in Figure 15. Figure 16 further shows the current waveforms present in the various branches of the 2-phase synchronous Buck regulators operating in the continuous mode. * Place the loop of M1, M3 and CIN1 in a compact area. This loop conducts high pulsating current and its area needs to be minimized. Place M2, M4 and CIN2 in the same way. * Place CIN1 and CIN2 within the distance of 1cm. Longer distance may cause a large resonant loop. * Connect the negative plates of COUT1 and CDR1 to PGND1 before it joins PGND2 at the ground plane. Connect COUT2 and CDR2 in the same way so that power grounds are separated before they meet at a single point.
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10 4.7F 5V 1F PGND1 1F 14 13 15 16 20 18 19 11 12 7 30 10 8 20k 100pF 680pF 0.022F 0.01F 1nF
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M2 0.22F
L2 1H
+
M4 D2 B340A
COUT2 470F 4V
VOUT1 1.8V 10A 22F 6.3V X7R
514k VIN VCC
39k
R3 20k 1%
56pF 5V 100k PGOOD
10k
11k
R4 10k 1%
* Cover the board area under the LTC3708 with a SGND plane and solder the back of the IC to this plane. Separate SGND from the power ground and connect all signal components (ITH, VFB, ION, VCC, EXTLPF, INTLPF, VRNG, TRACK and RUN/SS) to the SGND plane before it joins PGND. Connect SGND to the gound plane at a single point. * Run SENSE+ and SENSE- across the bottom MOSFET (or RSENSE when a separate current sensing resistor is used) with Kelvin connection (Figure 17). Route SENSE+ and SENSE- together with minimum PC trace separation. The filter capacitor (when used) between SENSE+ and SENSE- should be as close to the LTC3708 as possible. * Keep the high dV/dt nodes SW, TG and BOOST away from sensitive small-signal nodes.
3708i
19
LTC3708
APPLICATIO S I FOR ATIO
COUT1
L1
D1 SENSE1- TRACK1 PGND1 M3 VRNG1 VCC LTC3708 DRVCC CDR2 BG2 M4 PGND2 RUN/SS VRNG2 SGND CSS CVCC 5V
M1 CIN1 VIN CIN2 M2 5V CDR1
L2
D2 SENSE2+ BOOST2 COUT2 CB2 SW2 TG2 ITH2 R4 VFB2 R2 INTLPF ION2
Figure 15. LTC3708 Layout Diagram
* Connect the decoupling capacitors CDR1 and CDR2 close to the DRVCC and PGND pins. Connect CB1 and CB2 close to the BOOST and SW pins. * Connect the decoupling capacitor CVCC right across the VCC pin and SGND plane. Connect the EA compensation components close to the ITH pins. Connect the PLL loop filter close to the EXTLPF and INTLPF pins. Connect the ION decoupling capacitor close to the ION pins.
20
U
RON1 FCB TG1 SW1 CB1 BOOST ION1 PGOOD VFB1 ITH1 R1 R3 SENSE1+ EXTLPF BG1 SENSE2- TRACK2 RON2
3708 F15
W
UU
* Flood all unused areas on all layers with copper. Flooding will reduce the temperature rise of the power components. You can connect the copper area to any DC net (VIN, VOUT, GND or to any other DC rail in your system).
3708i
LTC3708
APPLICATIO S I FOR ATIO
CERAMIC
VIN RIN CIN
+
BOLD LINES INDICATE HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MINIMUM LENGTH.
CERAMIC
Figure 16. Branch Current Waveforms
D D D D
G S S S RSENSE MOSFET SENSE + SENSE - SENSE + SENSE -
3708 F17
(17a) Sensing the Bottom MOSFET
U
SW1 L1 VOUT1 D1 COUT1
W
UU
+
RL1
SW2
L2
VOUT2
D2
COUT2
+
RL2
3708 F16
(17b) Sensing a Resistor
Figure 17. Kelvin Sensing
3708i
21
LTC3708
TYPICAL APPLICATIO S
High Efficiency, Dual Output Converter with External Frequency Synchronization
VIN 3.3V TO 28V
VOUT1 2.5V 15A
L1 1.4H COUT1 + 330F 4V x2 12.1k 1% 19.1k 1% D1 B340A
M1 CB1 0.22F
DRVCC PGOOD VCC TG1 TG2 BOOST2 BOOST1 SW1 SENSE1+ BG1 LTC3708 SW2 SENSE2+ BG2 SENSE2- PGND2 fIN
M3
SENSE1- PGND1
VIN
RON1 1.5M 33k 10k 0.01F 180pF CSS 0.1F
6.04k 1%
6.04k 1% 0.01F
VFB1 VFB2 TRACK2 FCB ION1 ION2 ITH1 ITH2 INTLPF EXTLPF RUN/SS TRACK1 VRNG2 SGND VRNG1
COUT1: SANYO POSCAP 4TPD330M COUT2: SANYO POSCAP 2R5TPD470M
DB1, DB2: CMDSH-3 L1, L2: PANASONIC ETQP3H1R4
22
+
U
5V 10 DB1 1F 4.7F 100k DB2
CIN 10F 50V x4
M2 CB2 0.22F
L2 1.4H D2 B340A
+
M4 12.1k 1% FREQ = 210kHz VIN RON2 1M 1k 100k 33k 0.1F 5V 180pF
3708 TA01
COUT2 470F 2.5V x2
VOUT2 1.8V 15A
6.04k 1% 0.01F
25k
M1, M2: RENESAS HAT2168 M3, M4: RENESAS HAT2165
3708i
LTC3708
PACKAGE DESCRIPTIO
5.50 0.05 4.10 0.05 3.45 0.05 (4 SIDES)
RECOMMENDED SOLDER PAD LAYOUT 5.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 0.00 - 0.05
NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS
U
UH Package 32-Lead Plastic QFN (5mm x 5mm)
(Reference LTC DWG # 05-08-1693)
0.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 31 32 0.40 0.10 1 2 0.23 TYP (4 SIDES) 3.45 0.10 (4-SIDES)
(UH) QFN 0603
0.200 REF
0.25 0.05 0.50 BSC
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
3708i
23
LTC3708
TYPICAL APPLICATIO
VIN 5V
Dual Phase, Single Output 600kHz Converter with Voltage Tracking
+
CIN1 100F 6.3V
CIN2-CIN7 4.7F 6.3V x6
TRACK BAT54A 10 BOOST2 VCC 1F 1F PGND2 1F PGND1
VOUT 1V 30A COUT1 1F 6.3V
L1 0.19H
+
COUT3 470F 2.5V x2
D1 B340A
100k R1 VCC 10k 0.1% R2 15k 0.1% 0.01F 274k VIN
22k
CIN1: SANYO OS-CON 6SVP100M COUT3-COUT6: SANYO POSCAP 2R5TPD470M L1, L2: PANASONIC ETQP4LR19 M1 TO M4: RENESAS HAT2165
RELATED PARTS
PART NUMBER LTC1778 LTC3728 LTC3729 LTC3731 LTC3778 DESCRIPTION Wide Operating Range, No RSENSE Step-Down Controller Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator 550kHz, PolyPhase(R), High Efficiency, Synchronous Step-Down Switching Regulator 3-Phase, 600kHz, Synchronous Buck Switching Regulator Controller Wide Operating Range, No RSENSE Step-Down Controller COMMENTS Single Channel, GN16 Package Fixed Frequency, Dual Output Fixed Frequency, Single Output, Up to 12-Phase Operation 3-Phase, Single Output Single Channel, Separate VON Programming
PolyPhase is a registered trademark of Linear Technology Corporation
24
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
U
M1 M3 17 4 31 21 VCC TRACK1 FCB DRVCC 27 TG1 TG2 28 BOOST1 BOOST2 0.22F 26 SW1 SW2 25 SENSE2+ SENSE1+ 22 LTC3708 BG2 BG1 100pF 24 SENSE2- SENSE1- 23 PGND1 PGND2 32 VRNG1 VRNG2 29 ION1 ION2 3 VFB2 VFB1 6 TRACK2 PWRGD 9 EXTLPF INTLPF 2 ITH1 ITH2 RUN/SS 1000pF VCC 220pF 22.1k 1 SGND 5 220pF 0.01F 0.01F 10k 14 13 15 16 20 18 19 11 12 7 30 10 8 VRNG1 274k VIN VIN 100k PGOOD 100pF M4 0.22F M2 L2 0.19H COUT4 470F D2 B340A 2.5V x2
+
COUT2 1F 6.3V
1nF
3708 TA02
3708i LT/TP 1103 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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